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description the a8519 is a multi-output led driver for small-size lcd backlighting. it integrates a current-mode boost converter with internal power switch and four current sinks. the boost converter can drive up to 44 white leds, 11 led per string, at 100 ma. the led sinks can be paralleled together to achieve higher led currents up to 400 ma. the a8519 operates from a single power supply from 4.5 to 40 v, which allows the part to withstand load dump conditions encountered in automotive systems. the a8519 can control led brightness through a digital (pwm) signal. an led brightness contrast ratio of 10,000:1 can be achieved using pwm dimming at 100 hz; a higher ratio of 100,000:1 is possible when using a combination of pwm and analog dimming. if required, the a8519 can drive an external p-channel mosfet to disconnect input supply from the system in the event of a fault. the a8519 provides protection against output short, overvoltage, open or shorted diode, open or shorted led pin, and overtemperature. a cycle-by-cycle current limit protects the internal boost switch against high-current overloads. a8519-ds, rev. 7 features and benefits ? automotive aec-q100 qualified ? fully integrated 42 v mosfet for boost converter ? fully integrated led current sinks ? w ithstands surge input up to 40 v in for load dump ? operates down to 3.9 v in (max) for idle stop ? drives four strings of leds ? maximum output voltage 40 v ? up to 1 1 white leds in series ? drive current for each string is 100 ma ? programmable boost switching frequency (200 khz to 2.15 mhz) ? synchronized boost switching frequency option (260 khz to 2.3 mhz) ? dithering of boost switching frequency to reduce emi ? extremely high led contrast ratio ? 10,000:1 using pwm dimming alone ? 100,000:1 when combining pwm and analog dimming wide input voltage range, high-efficiency, fault-tolerant led driver packages: typical application diagram not to scale a8519 and a8519-1 continued on the next page continued on the next page v> v out in c in c out1 c out2 c vdd r pu c p l1 q1 d1 r adj r sc optional c z r z r iset v in apwm agnd gnd pgnd vdd r ovp v c pwm led4 led1 ovp vin gate sw vout fa ult vsense r fset clkout iset fset a8519 led2 led3 comp typical application circuit showing vout-to-ground short protection using optional p-channel mosfet applications: ? automotive infotainment backlighting ? automotive cluster ? automotive center stack 28-pin qfn with exposed thermal pad (suffix et) 20-pin tssop with exposed thermal pad (suffix lp) october 24, 2016
2 absolute maximum ratings [2] characteristic symbol notes rating unit ledx pins v ledx x = 1, 2, 3, or 4 C0.3 to 40 v ovp pin v ovp C0.3 to 40 v vin, vout pins v in, v out C0.3 to 40 v vsense, gate pins v sense, v gate v in C7.4 to v in +0.4 v sw pin [3] v sw continuous C0.6 to 42 v t < 50 ns C1 to 48 v fault pin v fault C0.3 to 40 v apwm, pwm, clkout, comp, fset, iset, vdd pins C0.3 to 5.5 v operating ambient temperature t a k temperature range C40 to 125 c maximum junction temperature t j(max) 150 c storage temperature t stg C55 to 150 c 2 operation at levels beyond the ratings listed in this table may cause permanent damage to the device. the absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the electrical characteristics table is not implied. exposure to absolute maximum-rated conditions for extended periods may affect device reliability. 3 sw dmos is self-protecting and will conduct when v sw exceeds 48 v. the a8519 has a synchronization pin that allows boost switching frequencies to be synchronized in the range of 260 khz to 2.3 mhz. the high switching frequency allows the converter to operate above the am radio band. the ic contains a clock output pin that allows other converters to be synchronized to the a8519s boost switching frequency. the a8519 employs hysteresis control to help regulate the led current at extremely short pwm on-time. the a8519-1 is identical to the a8519, except that it uses a smaller hysteresis window to reduce output voltage ripple during pwm dimming. ? excellent input voltage transient response at lowest pwm duty cycle ? gate driver for optional p-channel mosfet input disconnect switch ? led current accuracy 0.7% ? led string current-matching accuracy 0.8% ? protection against: ? shorted boost switch, inductor or output capacitor ? shorted fset or iset resistor ? open or shorted led pins and led strings ? open boost diode ? overtemperature fea tures and benefits (continued) description (continued) selection guide part number operating ambient temperature range t a (c) hysteresis window package packaging [1] leadframe plating a8519klptr-t C40 to 125 350 mv 20-pin tssop with exposed thermal pad 4000 pieces per reel 100% matte tin a8519kettr-r C40 to 125 350 mv 28-pin 5 5 mm qfn with exposed ther- mal pad and sidewall plated 1500 pieces per reel 100% matte tin a8519klptr-t-1 C40 to 125 150 mv 20-pin tssop with exposed thermal pad 4000 pieces per reel 100% matte tin A8519KETTR-R-1 C40 to 125 150 mv 28-pin 5 5 mm qfn with exposed ther- mal pad and sidewall plated 1500 pieces per reel 100% matte tin 1 contact allegro for additional packing options. wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
3 table of contents specifications 2 selection guide 2 absolute maximum ratings 2 thermal characteristics 3 functional block diagram 4 pinout diagrams and terminal list 5 characteristic performance 10 functional description 12 enabling the ic 1 2 powering up: led pin short-to-gnd check 12 powering up: boost output undervoltage 13 soft-start function 14 frequency selection 14 sync 14 led current setting and led dimming 15 pwm dimming 16 apwm pin 17 extending led dimming ratio 18 analog dimming 18 led short detect 19 overvoltage protection 20 boost switch overcurrent protection 21 input overcurrent protection and disconnect switch 22 setting the current sense resistor 22 input uvlo 22 vdd 23 shutdown 23 dithering feature 24 fault protection during operation 25 application information 28 design example 32 package outline drawings 33 thermal characteristics: may require derating at maximum conditions; see application information. characteristic symbol test conditions [1] value unit package thermal resistance r ja lp package on 2-layer 3 in 2 pcb 40 c/w et package on 2-layer 3 in 2 pcb contact factory c/w lp package on 4-layer pcb based on jedec standards 29 c/w et package on 4-layer pcb based on jedec standards 32 c/w 1 additional thermal information available on the allegro website. wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
4 functional block diagram fa ul t block iset block gate off led driver block diode open se ns e tsd ovp2 vout ovp e nabl e block pwm block regulator uv lo block input current sense ampli?er ga te pwm vsense vi n vi n agnd agnd agnd sw fset ag nd 1.235 v reference nmos driver driver ci rc ui t internal soft start block vout hyst. control ovp sense open/short led detect os ci llat or in ternal v cc in ternal v cc frequency dithering le d1 le d2 le d3 le d4 apwm iset agnd v ref v ref vdd i adj ag nd fault pgnd pgnd co mp clkout + ? + ? + ? + ? ocp2 current sense error ampli?er wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
5 pinout diagrams terminal list table pin number name function lp et 1 18 comp output of the error amplifier and compensation node. connect an rz-cz-cp network from this pin to gnd for control loop compensation. 2 19,20,21 pgnd power ground for internal n-channel mosfet switching device. connect to pcb ground plane. 3 22 ovp overvoltage protection. connect external resistor from vout to this pin to adjust the overvoltage protection level. 4 23 vout connect directly to boost output voltage. 5 25,26 sw the drain of the internal n-channel mosfet switching device of the boost converter. 6 27 gate output gate driver pin for external p-channel mosfet control. 7 28 vsense connect this pin to the negative sense side of the current sense resistor rsc. the threshold voltage is measured as v in -v sense . there is also fixed current sink to allow for trip threshold adjustment. 8 1 vin input power to the ic as well as the positive input used for current sense resistor. 9 3 fault the pin is an open-drain type configuration that will be pulled low when a fault occurs. connect a 100 k w resistor between this pin and desired logic level voltage. 10 4 clkout logic output representing the switching frequency of internal boost oscillator. this allows other converters to be synchronized to the same frequency (with the same frequency dithering, if applicable) 11 5 vdd output of internal ldo (bias regulator). connect a 1 f decoupling capacitor between this pin and gnd. 12 6 apwm analog trimming option or dimming. applying a digital pwm signal to this pin adjusts the internal i iset current. 13 7 pwm enables the ic when this pin is pulled high. also serves to control the led intensity by using pulse-width modulation. typical pwm dimming frequency is in the range of 100 to 400 hz. 14 8 fset frequency/synchronization pin. a resistor r fset from this pin to gnd sets the switching frequency (with dithering superimposed). it can also be used to synchronize two or more converters in the system to an external frequency between 260 khz and 2.3 mhz (dithering is disabled in this case). 15 9 iset connect r iset resistor between this pin and gnd to set the desired led current setting. 16 10,11 agnd led current ground. connect to pcb ground plane. 17,18, 19,20 13,14, 15,16 led 1-4 led current sinks #1 to 4. connect the cathode of each led string to associated pin. unused led pin must be terminated to gnd through a 3.09 k? resistor. C 2,12, 17,24 nc no connect. leave open or connect to gnd. C C pad exposed pad of the package providing enhanced thermal dissipation. this pad must be connected to the ground plane(s) of the pcb with at least 8 vias, directly in the pad. 1 comp led4 2 pgnd led3 3 ovp led2 4 vout led1 5 sw agnd 6 gate iset 7 vsense fset 8 vin pwm 9 fault apwm 10 clkout vdd pad 11 12 13 14 15 16 17 18 19 20 2 vin 3 fault 4 clkout 5 vdd 6 apwm 7 pwm 8fset 9iset 10 agnd 11 agnd 12nc 13led1 14led2 15 led3 16 led4 17 nc nc 18 comp 19 pgnd 20 pgnd 21 pgnd 22 ovp 23 vout 24 nc 25 sw 26 sw 27 28 gate 1 vsense 28-pin qfn with exposed thermal pad (suffix et) 20-pin tssop with exposed thermal pad (suffix lp) wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 electrical characteristics [1] : unless otherwise specified, specifications are valid at v in = 16 v, t a = 25c; indicates specifications guaranteed over the full operating temperature range with t a = t j = -40c to 125c; typical specifications are at t a = 25c characteristic symbol test conditions min. typ. max. unit input voltage input voltage range [3] v in 4.5 C 40 v uvlo start threshold v uvlorise v in rising C C 4.35 v uvlo stop threshold v uvlofall v in falling C C 3.9 v uvlo hysteresis v uvlohys 300 450 600 mv input supply current input quiescent current i q v pwm = v ih , f sw = 2 mhz C 8 15 ma input sleep supply current i sleep v in = 16 v, v pwm = v sync = 0 v C 2.0 10 a input logic levels (pwm, apwm) input logic level low v il C C 0.4 v input logic level high v ih 1.5 C C v pwm input pull-down resistor r en v pwm = 5 v 60 100 140 k? apwm input pull-down resistor r apwm v pwm = v ih 60 100 140 k? apwm apwm frequency [2] f apwm 40 C 1000 khz output logic levels (clkout) output logic level low v ol 5 v < v in < 40 v C C 0.3 v output logic level high v oh 5 v < v in < 40 v 1.8 C C v error amplifier source current i ea(source) v comp = 1.5 v C C600 C a sink current i ea(sink) v comp = 1.5 v C +600 C a comp pin pull-down resistance r comp fault = 0, v comp = 1.5v C 1.4 C k? overvoltage protection ovp pin voltage threshold v ovp(th) ovp pin connected to v out 7 8.3 9.5 v ovp pin sense current threshold i ovp(th) current into ovp pin 190 200 210 a ovp pin leakage current i ovp(lkg) v in = 16 v, pwm = l C 0.1 1 a ovp accuracy C C 5 % undervoltage protection threshold v uvp(th) measured at vout pin when r ovp = 160 kw [2] C 3 C v measured at vout pin when r ovp = 0 C 0.55 0.7 v secondary overvoltage protection v ovp(sec) measured at sw pin 42 45 48 v continued on the next page 1 for input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. 3 minimum v in = 4.5 v is only required at startup. after startup is completed, ic can continue to operate down to v in = 3.9 v 4 led current is trimmed to cancel variations in both gain and iset voltage wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
7 boost switch switch on-resistance r sw i sw = 0.75 a, v in = 16 v 100 250 500 m switch leakage current i sw(lkg) v sw = 16 v, v pwm = v il C 0.1 1 a switch current limit i sw(lim) 3 3.65 4.5 a secondary switch current limit [2] i sw(lim2) higher than max i sw(lim) under all conditions part latches when detected C 4.9 C a minimum switch on-time t sw(on) 45 65 85 ns minimum switch off-time t sw(off) C 65 85 ns oscillator frequency oscillator frequency [5] f sw r fset = 10 k 1.95 2.15 2.35 mhz r fset = 21.5 k 0.9 1 1.1 mhz r fset = 110 k C 200 C khz oscillator frequency dithering range f sw_dith r fset = 10 k C 5 C % dithering modulation frequency f sw_mod r fset = 10 k C 12.5 C khz fset pin voltage v fset a8519, r fset = 10 k C 1.02 C v a8519-1, r fset = 10 k C 1.07 C v synchronization sync input logic level v syncl fset pin logic low C C 0.4 v v synch fset pin logic high 2 C C v synchronized pwm frequency f sw(sync) 260 C 2300 khz synchronization input min. off-time t sync(off) 150 C C ns synchronization input min. on-time t sync(on) 150 C C ns led current sinks ledx accuracy [4] err led r iset = 8.33 kw C 0.7 3 % ledx matching ledx i iset = 120 a C 0.8 2 % ledx regulation voltage v ledx v led1 = v led2 = v led3 = v led4 , i iset = 120 a 750 850 975 mv iset to i ledx current gain a iset i iset = 120 a 696 710 727 a/a iset pin voltage v iset 0.987 1.017 1.047 v allowable iset current i iset 20 C 144 a v ledx short detect v ledx(sc) while led sinks are in regulation; sensed from v ledx to agnd 4.7 5.2 5.7 v led startup ramp time [2] t ss time duration before all led channels come into regulation, or ovp is tripped C 20 C ms electrical characteristics [1] : unless otherwise specified, specifications are valid at v in = 16 v, t a = 25c; indicates specifications guaranteed over the full operating temperature range with t a = t j = -40c to 125c; typical specifications are at t a = 25c characteristic symbol test conditions min. typ. max. unit continued on the next page 1 for input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. 3 minimum v in = 4.5 v is only required at startup. after startup is completed, ic can continue to operate down to v in = 3.9 v 4 led current is trimmed to cancel variations in both gain and iset voltage 5 f sw measurements were taken with dithering function is disabled. wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
8 pwm dimming maximum pwm dimming until off- time [2] t pwml measured while pwm = low, during dimming control and internal references are powered on (exceeding t pwml results in shutdown) C 32750 C f sw cycles minimum pwm on-time t pwmh(min1) first cycle when powering up ic (v pwm = 0 to 3.3 v) C 0.75 2 s t pwmh(min) subsequent pwm pulses C 0.5 1 s pwm high to led on delay t d(pwmon) time between pwm going high and when led current reaches 90% of maximum (v pwm = 0 to 3.3 v) C 0.2 0.5 s pwm low to led off delay t d(pwmoff) time between pwm going low and when led current reaches 10% of maximum (v pwm = 3.3 to 0 v) C 0.36 0.5 s hysteresis control hysteresis window (a8519) v hyst measured at vout pin when pwm = h to l C 0.35 C v hysteresis window (a8519-1) v hyst1 measured at vout pin when pwm = h to l C 0.15 C v gate pin gate pin sink current i g(sink) v gate = v in , no input ocp fault C C113 C a gate pin source current i g(source) v gate = v in C 6 v, input ocp fault tripped C 6 C ma gate shutdown delay when overcurrent fault is tripped [2] t fault v in C v sense = 200 mv, monitored at fault pin C C 3 s gate voltage v gate measured between gate and vin when gate is on C C6.7 C v vsense pin vsense pin sink current i vsense 17.2 21.5 25.8 a vsense trip point v sense(trip) measured between vin and vsense, r adj = 0 95 110 125 mv fault pin fault pull-down voltage v fault i fault = 1 ma C C 0.5 v fault pin leakage current i fault(lkg) v fault = 5 v C C 1 a thermal protection (tsd) thermal shutdown threshold [2] t sd temperature rising 155 170 C c thermal shutdown hysteresis [2] t sd(hys) C 20 C c electrical characteristics [1] : unless otherwise specified, specifications are valid at v in = 16 v, t a = 25c; indicates specifications guaranteed over the full operating temperature range with t a = t j = -40c to 125c; typical specifications are at t a = 25c characteristic symbol test conditions min. typ. max. unit 1 for input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. 3 minimum v in = 4.5 v is only required at startup. after startup is completed, ic can continue to operate down to v in = 3.9 v 4 led current is trimmed to cancel variations in both gain and iset voltage wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
9 v> v out in c in c out1 c out2 c vdd r pu c p l1 q1 d1 r adj r sc optional c z r z r iset v in apwm agnd gnd pgnd vdd r ovp v c pwm led4 led1 ovp vin gate sw vout fa ult vsense r fset clkout iset fset a8519 led2 led3 comp c in c out c vdd r pu c p l1 r1* c sw l2 d2 d2* c z r z r iset v in apwm *notes: input disconnect switch is not necessary in this case to protect against vout-to-ground short. r1 and d2 are used to provide a leakage path so the ovpp in is above 100 mv during startup. otherwise, the ic would assume an vout-to-gnd short and not proceed with soft start. agnd gnd pgnd vdd r ovp v c pwm led4 led1 ovp vin gate sw vout fa ult vsense output: 3 wled in series (~10 v) r fset clkout iset fset led2 led3 comp a8519 typical application showing boost configuration with input disconnect switch to protect against vout-to-ground short typical application showing sepic configuration for flexible input/output voltage ratio wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
10 characteristic performance 8 80.00 81.00 82.00 83.00 84.00 85.00 86.00 87.00 88.00 89.00 10 12 14 16 10 4 le d 9 4 led 8 4 led 7 4 led eff % ef?ciency at 60 ma/channel for various led con?gurations v( v) in efficiency measurement a8519 evaluation board efficiency versus input voltage while disconnect switch and snubber circuit are used 0.1 78.00 80.00 82.00 84.00 86.00 88.00 90.00 92.00 0.2 0.3 0.4 10 4 le d 9 4 led 8 4 led 7 4 led eff % ef?ciency at v= 12 v for various led con?gurations in to tal led current (a) a8519 evaluation board efficiency versus total led current while disconnect switch and snubber circuit are used startup waveforms start up at 100% pwm dimming, v in = 7 v, 4 channels, 10 leds/channel, 60 ma/channel; time base = 10 ms/div start up at 0.02% pwm dimming, v in = 7 v, 4 channels, 10 leds/channel, 60 ma/channel; time base = 10 ms/div higher efficiency can be achieved by: ? using an inductor with low dcr. ? using lower forward voltage drop and smaller junction capacitance schottky diode. ? removing the snubber circuit; however , this might compromise the emi performance. ? shorting out the disconnect switch and the input current sense resistor; however , this will eliminate the output short-to-gnd protection feature. ? lowering switching frequency . this will significantly improve the efficiency; however, to avoid the emi am band limits, careful switching frequency selection is required. in addition, a larger inductor will be needed. v out v sw i led(total) v out v sw i led(total) wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
11 transient response to step change in pwm dimming from pwm = 0.1% to pwm = 100% at 4 channels, 60 ma/channel, v in = 12 v; time base = 50 ms/div from pwm = 100% to pwm = 0.1% at 4 channels, 60 ma/channel, v in = 12 v; time base = 50 ms/div transient response to step change in v in voltage from v in = 16 v to v in = 5.5 v, 4 channels, 60 ma/channel, pwm = 100%; time base = 50 ms/div from v in = 5.5 v to v in = 16 v, 4 channels, 60 ma/channel, pwm = 100%; time base = 50 ms/div v sw v out i led(total) v sw v out i led(total) v sw v out i led(total) v in v sw v out i led(total) v in wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
12 enabling the ic the ic turns on when a logic high signal is applied on the pwm pin with a minimum duration of t pwmh for the first clock cycle, and the input voltage present on the vin pin is greater than 4.35 v to clear the uvlo threshold. before the leds are enabled, the a8519 driver goes through a system check to see if there are any possible fault conditions that might prevent the system from functioning correctly. also if the fset pin is pulled low the ic will not power up. more information on the fset pin can be found in the synchronization section of the datasheet. functional description figure 1: power up diagram showing pwm, iset, and vdd voltages and total led current figure 2: power up diagram showing disconnect v gate , v led1 , v iset , and v pwm during led pins detect and regulation period 3.09 k 3.09 k 3.09 k use led1 channel only use four led channels agnd gnd agnd gnd led2 led2 led3 led3 led4 led4 led1 led1 led strings led string figure 3: channel select setup when the voltage threshold on vledx pins exceeds 120 mv, a delay between 3000 and 4000 clock cycles (1.5 to 2 ms) is used to determine the status of the pins. table 1: led detection duration for given switching frequency switching frequency detection time 2 mhz 1.5 to 2 ms 1 mhz 3 to 4 ms 800 khz 3.75 to 5 ms 600 khz 5 to 6.7 ms all unused led pins should be connected with a 3.09 k? resis - tor to gnd. the unused pin, with the pull-down resistor, will be taken out of regulation at this point and will not contribute to the boost regulation loop. v pwm v iset i led(total) v vdd once the ic is enabled, there are only two ways to shut down the ic into low-power mode: 1. pull pwm pin to low for at least 32,750 clock cycles (approximately 16 ms at 2 mhz). 2. cut off the supply and allow v in to drop below uvlo fall- ing threshold (less than 3.9 v). powering up: led pin check once vin pin goes above uvlo and a high signal is present on the pwm pin, the ic proceeds to power up. the a8519 then enables the disconnect switch (gate) and checks to see if the led pins are shorted to ground and/or are not used. the led detect phase starts when the gate voltage of the disconnect switch is equal to v in C 3.3 v. figure 2 shows the relation of ledx pins with respect to the gate voltage of the disconnect switch (if used) during led detect phase, as well as the duration of the led detect for a switching frequency of 2 mhz. v gate v led1 led current regulation begins v pwm led detection period gate= vin - 3.3v gate otae i ped oer tan v v et wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
13 table 2: led detection voltage thresholds led pin voltage level led pin action less than 70 mv indicates a short to pcb gnd a8519 will not proceed with power up. 150 mv not used led string connected with the unused led pin is removed from operation 325 mv led pin in use none figure 4: led string detect occurs when all led strings are selected to be used led detection ire detect votae i aot 1 v en led pin 2 i not ed if an led pin is shorted to ground, the a8519 will not proceed with soft-start until the short is removed from the led pin. this prevents the a8519 from powering up and putting an uncon- trolled amount of current through the leds. figure 6: one led pin is shorted to gnd. the ic will not proceed with power up until led pin is released, at which point the led pin is checked to see if it is used. powering up: boost output undervoltage protection during startup, after the input disconnect switch has been enabled, the output voltage is checked through the ovp pin. if the sensed voltage does not rise above v uvp(th) , the output is assumed to be at fault and the ic will not proceed with soft-start. undervoltage protection may be caused by one of the following faults: ? output capacitor shorted to gnd ? boost inductor or diode open ? ovp sense resistor open after an output uvp fault has been detected, the a8519 immedi- ately shuts down but does not latch off. it will retry as soon as the uvp fault is removed. in case of output capacitor shorted to gnd fault, however, the high inrush current will also trip the input ocp fault. this causes the ic to shut down and latch off. to enable the ic again, the pwm pin must be pulled low for at least 32,750 clock cycles (about 16 ms at 2 mhz), then pulled high again. v led2 led current regulation begins v led1 v et v pm v led2 v led1 v et v pm led2 i not ed v led2 v led1 v et v pm ort i reoed ort i appied at led1 wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
14 soft-start function during startup, the a8519 ramps up its boost output voltage following a fixed ramp function. this technique limits the input inrush current and ensures the same startup time regardless of the pwm duty cycle. the soft-start process is completed when any one of the follow- ing conditions is met: 1. all led currents have reached their regulation tar gets, 2. output voltage has reached 93% of its ovp threshold, or 3. soft-start ramp time (t ss ) has expired. frequency selection figure 7: startup diagram showing the input current, output voltage, total led current, and switch node voltage synchronization the a8519 can also be synchronized using an external clock. at power-up, if the fset pin is held low, the ic will not power-up. only when the fset pin is tri-stated to allow for the pin to rise to about 1 v, or when a sync clock is detected, the a8519 will try to power up. the basic requirement of the sync signal is 150 ns minimum on-time and 150 ns minimum off-time as dictated by the requirements of pulse-width on- and off-times. figure 9 shows timing for a synchronization clock into the a8519 at 2.2 mhz. any pulse with a duty cycle of 33% to 66% at 2.2 mhz can be used to synchronize the ic. table 3 summarizes the duty cycle range at various synchronization frequencies. figure 8: switching frequency versus r fset resistor 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 01 0 20 30 40 50 60 70 80 90 100 11 0 resistance in k frequency in mhz figure 9: sync pulse on- and off-time requirements pulse width sync on time pulse width sync of ft ime 150 ns 150 ns 154 ns t= 454 ns the switching frequency on the boost regulator is set by a single resistor connected to the fset pin. the switching frequency can be can be anywhere from 200 khz to 2.15 mhz. figure 8 shows typical switching frequency in mhz for a given resistor value (in k?). the following equation can also be used to determine typi - cal switching frequency from fset resistance: f sw = 21.4/r fset + 0.008 where f sw is in mhz, r fset is in k. if a fault occurs during operation that will increase the switch- ing frequency, the fset pin is clamped to a maximum switching frequency of no more than 3.5 mhz. if the fset pin is shorted to gnd, the part will shut down. for more details, see the fault mode table on page 25. v out v sw i led(total) i in wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
15 table 3: sync pulse duty cycle range for selected switch- ing frequencies. sync pulse frequency duty cycle range 2.2 mhz 33% to 66% 2 mhz 30% to 70% 1 mhz 15% to 85% 600 khz 9% to 91% 300 khz 4.5% to 95.5% figure 10: synchronized fset pin and switch node sw voltage. figure 11: transition of the switch wave form when the sync pulse is detected. the a8519 is switching at 2 mhz, and the applied sync pulse is 1 mhz. the led current does not show any variation while the frequency changeover occurs. v out v fset i led(total) v sw suppose the a8519 is started up with a valid external sync sig- nal, but the sync signal is lost during normal operation. in that case, one of the following happens: ? if the external sync signal is high impedance (open), the a8519 continues normal operation after approximately 5 s, at the switching frequency set by r fset . no fault flag is generated. ? if the external sync signal is stuck low (shorted to ground), the a8519 will detect an fset-shorted-to-gnd fault. the fault pin is pulled low after approximately 10 s, and switching is disabled. once the fset pin is released or sync signal is detected again, the a8519 will proceed to soft-start. to prevent generating a fault when the external sync signal is stuck at low, the circuit shown in figure 12 can be used. when the external sync signal goes low, the a8519 will continue to operate normally at the switching frequency set by the r fset . no fault flag is generated. a8519 schottky barrier diode fset r fset 10.2 k 220 pf external synchronization signal figure 12: countermeasure to prevent external sync signal stuck-at-low fault. led current setting and led dimming the maximum led current can be up to 100 ma per chan- nel, and is set through the iset pin. connect a resistor, r iset , between this pin and gnd. to set i led calculate r iset as fol- lows: i = i a led set iset i = set r iset v iset r = iset (v a ) iset iset i led where i led current is in a and r iset is in . 2mhz operation 1mhz operation v out v fset i led(total) v sw wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
16 this sets the maximum current through the leds, referred to as the 100% current. table 4: led current setting resistors (values rounded to the nearest standard resistor value) standard closest r iset resistor values led current i led 7.15 k 100 ma per led 8.87 k 80 ma per led 11.8 k 60 ma per led 14.3 k 50 ma per led 17.8 k 40 ma per led pwm dimming the led current can be reduced from the 100% current level by pwm dimming using the pwm pin. when the pwm pin is pulled high, the a8519 turns on and all enabled leds sink 100% current. when pwm is pulled low, the boost converter and led sinks are turned off. the compensation (comp) pin is floated, and critical internal circuits are kept active. the typical pwm dimming frequencies fall between 200 hz and 1 khz. the a8519 is designed to deliver a maximum dimming ratio of 10,000:1 at pwm frequency of 100 hz. that means a minimum pwm duty cycle of 0.01%, or an on-time of just 1 s out of a period of 10 ms. figure 13: typical pwm diagram showing v out , i led and comp pin, as well as the pwm signal. (pwm dimming frequency is 500 hz 50% duty cyle.) figure 14: typical pwm diagram showing v out , i led , and comp pin, as well as the pwm signal. (pwm dimming frequency is 500 hz 1% duty cycle.) figure 15: rising edge pwm signal to total led current i led(total) turn-on delay; time base = 100 ns figure 16: falling edge pwm signal to total led current i led(total) turn-off delay; time base = 100 ns v out v comp i led(total) v pwm v out v comp i led(total) v pwm i led(total) v pwm i led(total) v pwm wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
17 the apwm pin is used in conjunction with the iset pin (see figure 17). this is a digital signal pin that internally adjusts the i iset current. the typical input signal frequency is between 40 khz and 1 mhz. the duty cycle of this signal is inversely proportional to the percentage of current that is delivered to the led (see figure 18). as an example, a system that delivers i led(total) = 240 ma would deliver i led(total) = 180 ma when an apwm signal with a duty cycle of 25% is applied. when this pin is not used it should be tied to agnd. figure 17: simplified block diagram of apwm iset block iset current mirror apwm iset current adjust block pwm apwm iset r iset led driver apwm pin high-pwm dimming ratio is acheived by regulating the output voltage during pwm off-time. the vout pin samples the output voltage during pwm on-time and regulates it during off-time. a hysteresis control loop brings vout higher by approximately 350 mv (150 mv for a8519-1) whenever it drops below the target voltage. in a highly noisy switching environment, it is necessary to insert an rc filter at the vout pin. a typical value of r = 10 k and c = 47 pf is recommended. another important feature of the a8519 is the pwm signal to led current delay. this delay is typically less than 500 ns, which allows for greater led current accuracy at low-pwm dimming duty cycles. the error introduced by led turn-on delay is partially offset by led turn-off delay. therefore, a pwm pulse width of under 1 s is still feasible, but the percentage error of led current will increase with narrower pulse width. 0 10 20 30 40 50 60 70 80 90 100 01 0203040506070809 01 00 normalized led current (% ) apwm duty cycle (%) figure 18: normalized led current vs. apwm duty cycle v in = 9 v, v out = ~22 v, r iset = 24 k, apwm = 200 khz 0 1 2 3 4 5 01 02030405060708 09 01 00 led current error (% of full scale) apwm duty cycle (% ) figure 19: error in led current vs. apwm duty cycle v in = 9 v, v out = ~22 v, r iset = 24 k, apwm = 200 khz to use the apwm pin as a trim function, the user should set the maximum output current to a value higher than the desired current by at least 5%. the led i iset current is then trimmed down to the appropriate desired value. another consideration is the limitation of the apwm signals duty cycle. in some cases, it might be more desirable to set the maximum i iset current to be 25% to 50% higher, thus allowing the apwm signal to have duty cycles that are between 25% and 50%. wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
18 figure 22: transition of output current level when a 50% duty cycle apwm signal is applied to the apwm pin, in conjunction with 50% duty cycle applied to the pwm pin. extending led dimming ratio the dynamic range of led brightness can be further extended by using a combination of pwm duty cycle, apwm duty cycle, and analog dimming method. for example, the following approach can be used to achieve a 50,000:1 dimming ratio at 200 hz pwm frequency: ? v ary pwm duty cycle from 100% down to 0.02% to give 5,000:1 dimming. ? w ith pwm duty cycle at 0.02%, vary apwm duty from 0% to 90% to reduce led current down to 10%. this gives a net effect of 50,000:1 dimming. analog dimming besides using apwm signal, the led current can also be reduced by using an external dac or another voltage source. connect r iset between the dac output and the iset pin. the limit of this type of dimming is dependant of the range of the iset pin. in the case of the a8519, the limit is 20 to 144 a. v apwm i led(total) v pwm figure 20: transition of total led current from 240 ma to 180 ma, when a 25% apwm signal is applied to the apwm pin. (dimming pwm = 100%) figure 21: transition of total led current from 180 ma to 240 ma, when a 25% apwm stops being applied to the apwm pin. (dimming pwm = 100%) v apwm i led(total) v pwm v apwm i led(total) v pwm applied although the apwm dimming function has a wide frequency range, if used strictly as an analog dimming function, it is recom- mended to use frequency ranges between 50 and 500 khz for best accuracy. the frequency range needs to be considered only if the user is not using apwm as a closed-loop trim function. it takes about 1 millisecond to change the actual led current due to propagation delay between the apwm signal and the i led(total) . wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
19 the led current can be adjusted using the following formula: where v iset is the iset pin voltage and v dac is the dac output voltage. when v dac is equal to 1 v , the output is strictly controlled by the r iset resistor. when v dac is higher than 1 v , the led cur- rent is reduced. when v dac is lower that 1 v , the led current is increased. led string short detect all ledx pins are capable of handling the maximum v out that the converter can deliver, thus allowing for ledx pin to v out protection in case of a connector short. in case some of the leds in an led string are shorted, the volt- age at the corresponding ledx pin will increase. any ledx pin that has a voltage exceeding v ledx(sc) will be removed from operation. this will prevent the ic from dissipating too much power by having a large voltage present on an ledx pin. i = iset v iset r iset r1 ? v ? v iset dac figure 25: disabling of led1 string when the led1 pin voltage is increased above 4.6 v i led(total) v led1 v pwm vdac r iset iset a8519 dac or voltage source agnd gnd gnd simpli?ed diagram of voltage led current control figure 23: typical application circuit using a dac to control the led current in the a8519 the iset current is controlled by the following formula: where v iset is the iset pin voltage and v dac is the dac output voltage. when the dac voltage is 0 v , the led current will be at its max- imum. to keep the internal gain amplifier stable, do not decrease the current through the r iset resistor to less than 20 a. below is a typical application circuit using a dac to control the led current using a two-resistor configuration. the advantage of this circuit is that the dac voltage can be higher or lower, thus adjusting the led current to a higher or lower value of the preset led current set by the r iset resistor. i = iset r iset v ? v iset dac vdac r1 r iset iset a8519 dac agnd gnd gnd simpli?ed diagram of voltage led current control figure 24: typical application circuit using a dac and r iset resistor to control the led current in the a8519 wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
20 figure 26: output of a8519 when disconnected from load during normal operation figure 27: typical ovp condition caused by an open led string figure 27 illustrates a typical ovp condition caused by an open led string. once ovp is detected, the boost stops switching, and the open led string is removed from operation. afterwards, v out is allowed to fall, the boost will resume switching, and the a8519 will resume normal operation. v out v sw v pwm i led(total) v out v sw v pwm i led(total) while the ic is being pwm dimmed, the ic will recheck the dis- abled led every time the pwm signal goes high to prevent false tripping of led short. this also allows for some self-correction if an intermittent led pin short-to-vout is present. at least one led must be in regulation for the led string short- detect protection to activate. in case all of the led pins are above regulation voltage (this could happen when the input voltage rises too high for the led strings), they will continue to operate normally. overvoltage protection the a8519 has output overvoltage protection (ovp) and open schottky diode protection (secondary ovp). the ovp pin has a threshold level of 8.3 v typical. a resistor can be used to set the output overvoltage protection threshold up to 40 v approxi- mately. this is sufficient for driving 11 white led in series. the formula for calculating the ovp resistor is shown below: where v ovp(th) = 8.3 v typical and i ovp(th) = 200 a typical. the ovp function is not a latched fault. if the ovp condition occurs during a load dump, the ic will stop switching but not shut down. there are several possibilities why an ovp condition is encoun- tered during operation, the two most common being an open led string and a disconnected output condition. figure 26 illustrates when the output of the a8519 is discon- nected from load during normal operation. the output voltage instantly increases up to ovp voltage level, and then the boost stops switching to prevent damage to the ic. when the output voltage decreases to a low value, the boost converter will begin switching. if the condition that caused the ov event still exists, ovp will be triggered again. r= ovp (v ? v ) ovp ovp(th) i ovp(th) wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
21 figure 30 shows the cycle-by-cycle current limit showing induc- tor current as a green trace. note the inductor current is truncated and as a result the output voltage is reduced as compared to normal operation shown for the 114 led configuration. boost switch overcurrent protection the boost switch is protected with cycle-by-cycle current limit- ing set at a minimum of 3 a. figure 29 illustrates the normal operation of the switch node (v sw ), inductor current, and output voltage (v out ) for a 114 led configuration. figure 29: normal operation of switch node (v sw ), inductor current, and output voltage (v out ) figure 30: cycle-by-cycle current limit v out v sw v pwm inductor current v out v sw inductor current v pwm current is truncated here the a8519 also has built-in secondary overvoltage protection to protect the internal switch in the event of an open-diode condi- tion. open schottky diode detection is implemented by detecting overvoltage on the sw pin of the device. if voltage on the sw pin exceeds the devices safe operating voltage rating, the a8519 disables and remains latched. to clear this fault, the ic must be shut down by either using the pwm signal or by going below the uvlo threshold on the vin pin. figure 28 illustrates open schottky diode protection while the ic is in normal operation. as soon as the switch node voltage (v sw ) exceeds 48 v, the ic will shut down. due to small delays in the detection circuit, as well as there being no load present, the switch node voltage (v sw ) will rise above the trip point voltage. figure 28: open schottky diode protection open diode detected v ot v v pm ledtotal when enabling the a8519 into an open-diode condition, the ic will first go through all of its initial led detection and will then check the boost output voltage. at that point, the open diode is detected. wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
22 input overcurrent protection and disconnect switch the primary function of the input disconnect switch is to protect the system and the device from catastrophic input currents during a fault condition. if the input current level goes above the preset current limit threshold, the part will be shut down in less than 3 sthis is a latched condition. the fault flag is also set low to indicate a fault. this protection feature prevents catastrophic failure in the system due to a short of the inductor, inductor short to gnd, or short at the output gnd. figure 33 illustrates the typical input overcur- rent fault condition. as soon as input ocp limit is reached, the part disables the gate of the disconnect switch q1. during startup when q1 first turns on, an inrush current flows through q1 into the output capacitance. if q1 turns on too fast (due to its low gate capacitance), the inrush current may trip input ocp limit. in this case, an external gate capacitance c g is added to slow down the turn-on transition. typical value for c g is around 4.7 to 22 nf. do not make c g too large, since it also slows down the turn-off transient during a real input ocp fault. r sc c g q1 v in vin gnd vsense r adj i adj to l1 a8519 gate figure 32: typical circuit showing implementation of input disconnect feature figure 33: startup into output shorted to gnd fault. input ocp tripped at 4 a (r sc = 0.024 w, r adj =383 ) pwm v gate input current figure 31: secondary boost switch ocp there is also a secondary current limit (i sw(lim2) ) that is sensed through the boost switch. this current limit, once detected, immediately shuts down the a8519. the level of this current limit is set above the cycle-by-cycle current limit to protect the switch from destructive currents when boost inductor is shorted. figure 31 shows the secondary boost switch ocp. once this limit is reached, the a8519 will immediately shut down. v out v sw v pwm inductor current wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
23 vdd the vdd pin provides regulated bias supply for internal circuits. connect a capacitor with a value of 1 f or greater to this pin. the internal ldo can deliver no more than 2 ma of current with a typical vdd voltage of about 3.5 v, enabling this pin to serve as the pull-up voltage for the fault pin. shutdown if pwm pin is pulled low for more than t pwml (32,750 clock cycles), the device enters shutdown mode and clears all internal fault registers. as an example, at 2 mhz clock frequency, it will take approximately 16.3 ms to shut down the ic into the low power mode. when shut down, the ic will disable all current sources and wait until the pwm goes high to re-enable the ic. figure 35 depicts the shutdown using the pwm enable, showing the 16.3 ms delay between pwm signal and when the vdd and gate of disconnect switch turn off. figure 35: shutdown using the pwm enable v vdd v gate v pwm i led(total) setting the current sense resistor as shown in figure 32: v in C v sense = v sc + i adj r adj or i sc = ((v in C v sense ) C i adj r adj )/r sc where v sc = the voltage drop across r sc . the typical threshold for the current sense is v in C v sense = 110 mv when r adj is 0 w . the a8519 can have this voltage trimmed using the r adj resistor. it is recommended to set trip point to be above 3.65 a to avoid conflicts with the cycle-by-cycle current limit typical threshold. a sample calculation is done below for 4.25 a of input current. calculated max value of sense resistor r sc = 0.11 v / 4.25 a = 0.0259 . the r sc chosen is 0.024 , a standard value. therefore, the volt - age drop across r sc is: r= adj v= 4.25 a 0.024 = 0.102 v sc vC v vsense(trip) sc i adj = 372 r= adj 0.11 v C 0.102 v 21.5 a input uvlo when v in and v sense rise above v uvlorise threshold, the a8519 is enabled. the a8519 is disabled when v in falls below v uvlofall threshold for more than 50 s. this small delay is used to avoid shutting down because of momentary glitches in the input power supply. figure 34 illustrates a shutdown due to a falling input voltage (v in ). when v in falls below 3.90 v, the ic will shut down. figure 34: shutdown with falling input voltage v out v in v vdd i led(total) wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
24 figure 38: output voltage ripple frequency due to dithering = 12.4 khz at v in = 12 v, and pwm ratio = 100% figure 39: output voltage ripple amplitude due to dithering = 100 mv at v in = 12 v, and pwm ratio = 100% v sw v out v sw v out dithering feature to minimize the switching frequency harmonics, a dithering feature is implemented in a8519. this feature simplifies the input filters needed to meet the automotive cispr 25 conducted and radiated emission limits. the dithering sweep is internally set at 5%. the switching frequency will ramp from 0.95 times the programmed frequency to 1.05 times the programmed frequency. the rate or modulation at which the frequency sweeps is gov- erned by an internal 12.5 khz triangle pattern. figure 36: minimum dithering switching frequency = 2.02 mhz at v in = 12 v, and pwm ratio = 100% figure 37: maximum dithering switching frequency = 2.23 mhz at v in = 12 v, and pwm ratio = 100% wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
25 fault protection during operation the a8519 series devices constantly monitor the state of the system to determine if any fault conditions occur during normal operation. the response to a triggered fault condition is sum- marized in the table below. there are several points at which the a8519 monitors for faults during operation. the locations are input current, switch current, output voltage, switch voltage, and led pins. (note: some protection features might not be active during startup to prevent false triggering of fault conditions.) the detectable fault conditions are: ? open led pin ? shorted led pin to gnd ? open or shorted inductor ? open or shorted boost diode ? shorted inductor ? v out short to gnd ? sw pin shorted to gnd ? iset pin shorted to gnd ? input disconnect switch source shorted to gnd note: some faults will not be protected if the input disconnect switch is not used. an example of this is v out short to gnd. wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
26 table 5: fault mode table fault name type active fault flag set description boost disconnect switch led sink drivers primary switch overcurrent protection (cycle- by-cycle current limit) auto- restart always no this fault condition is triggered when the sw current exceeds the cycle-by-cycle current limit, i sw(lim) .the present sw on-time is truncated immediately to limit the current. next switching cycle starts normally. off for a single cycle on on secondary switch current limit latched always yes when current through boost switch exceeds secondary sw current limit (i sw(lim2) ), the device immediately shuts down the disconnect switch, led drivers, and boost. the fault flag is set. to re-enable the part, the pwm pin needs to be pulled low for 32,750 clock cycles. off off off input disconnect current limit latched always yes the device is immediately shut off if the voltage across the input sense resistor is above the v vsense(trip) threshold. to re-enable the device, the pwm pin must be pulled low for 32,750 clock cycles. off off off secondary ovp latched always yes secondary overvoltage protection is used for open-diode detection. when diode d1 opens, the sw pin voltage will increase until v ovp(sec) is reached . this fault latches the ic. the input disconnect switch is disabled as well as the led drivers. to re-enable the part, the pwm pin needs to be pulled low for 32,750 clock cycles. off off off ledx pin short protection auto- restart startup no this fault prevents the part from starting up if any of the led pins are shorted. the part stops soft-start from starting while any of the led pins are determined to be shorted. once the short is removed, soft-start is allowed to start. off on off ledx pin open auto- restart normal operation no when an led pin is open, the device will determine which led pin is open by increasing the output voltage until ovp is reached. any led string not in regulation will be turned off. the device will then go back to normal operation by reducing the output voltage to the appropriate voltage level. on on off for open pins, on for all others iset short protection auto- restart always no fault occurs when the i iset current goes above 150% of max current. the boost will stop switching and the ic will disable the led sinks until the fault is removed. when the fault is removed, the ic will try to regulate to the preset led current. off on off fset short protection auto- restart always yes fault occurs when the fset current goes above 150% of max current. the boost will stop switching, disconnect switch will turn off, and the ic will disable the led sinks until the fault is removed. when the fault is removed, the ic will try to restart with soft-start. off off off overvoltage protection auto- restart always no fault occurs when ovp pin exceeds v ovp(th) threshold. the ic will immediately stop switching to try to reduce the output voltage. if the output voltage decreases, then the ic will restart switching to regulate the output voltage. stop during ovp event on on wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
27 fault name type active fault flag set description boost disconnect switch led sink drivers undervoltage protection auto- restart always yes device immediately shuts off boost and current sinks if the voltage at ovp pin is below v uvp(th) . it will auto- restart once the fault is removed. off on off led string short detection auto- restart always no fault occurs when the led pin voltage exceeds 5.2 v. once the led string short fault is detected, the led string above the threshold will be removed from operation. on on off for shorted pins, on for all others overtemperature protection auto- restart always no fault occurs when the die temperature exceeds the overtemperature threshold, typically 170c. off off off v in uvlo auto- restart always no fault occurs when v in drops below v uvlofall , typically below 3.9 v. this fault resets all latched faults. off off off wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
28 design example this section provides a method for selecting component values when designing an application using the a8519. assumptions: for the purposes of this example, the following are given as the application requirements: ? v in : 10 to 14 v ? quantity of led channels, #channels: 4 ? quantity of series leds per channel, #seriesleds: 10 ? led current per channel, i led : 60 ma ? led v f at 60 ma: 3.2 v ? f sw : 2 mhz ? pwm dimming frequency 200 hz, 1% duty cycle step 1: connect led strings to pins led1, led2, led3, and led4. step 2: determine the led current set resistor r iset r = iset r = iset r = 11.8 k iset = 12 k (v a ) iset iset (1.017 710) i led 0.06 a an 11.8 k? resistor was chosen. step 3a: determining the ovp resistor. the ovp resistor is connected between the ovp pin and the output voltage of the converter. the first step is to determine the maximum voltage based on the led requirements. the regula- tion voltage for an led pin (v ledx ) of the a8519 is 850 mv. a 5 v headroom is added to give margin to the design due to noise and output voltage ripple. v out(ovp) = #seriesleds v f v led 5 v v out(ovp) = 10 3.2 v 0.850 v 5 v v out(ovp) = 37.85 v the ovp resistor is: r= ovp (v ? v ) out(ovp) ovp(th) i ovp(th) where both i ovp(th) and v ovp(th) values are from the datasheets electrical characteristics table. r= ovp r = 147.75 k ovp 37.85 ? 8.3 0.2 choose a value of resistor that is higher value than the calculated r ovp . in this case, a value of 158 k? was selected. below is the actual value of the minimum ovp trip level with the selected resistor. v out(ovp) = 158 k? 0.2 m step 3b: at this point, a quick check needs to be done to see if the conversion ratio is adequate for the selected frequency. where v d is the boost diode forward voltage, minimum off-time (t sw(off) ) is found in the datasheet: theoretical max v out = 1 ? d max(boost) d = 1?(85 ns 2.2 mhz) = 0.813 max(boost) d = 1? t f max(boost) sw(off) sw(max) ? v d v in(min) v d is the voltage drop of the boost diode. 10 v theoretical max v out = 1 ? 0.813 ? 0.4 = 53.1 v theoretical max v out value needs to greater than the value v out(ovp) . if this is not the case, the switching frequency of the boost converter is going to have to be reduced to meet the maxi- mum duty cycle requirements. step 4: inductor selection. the inductor needs to be chosen such that it can handle the neces- sary input current. in most applications, due to stringent emi requirements, the system needs to operate in continues conduc- tion mode throughout the whole input voltage range. application information wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
29 step 4a: determine the duty cycle. d = 1 ? max (v + v ) out(ovp) v in(min) d = 1 ? max (39.9 + 0.4) 10 = 0.75 d step 4b: determine the maximum and minimum input current to the system. the minimum input current will dictate the inductor value. the maximum current rating will dictate the current rating of the inductor. i = in(max) v i out(ovp) out v in(min) i = #channels i i = 4 0.06 0a = 0.240 a out out led a good approximation of efficiency can be taken from the efficiency curves located on page 10. a value of 90% is a good starting approximation. i = in(max) i = in(max) 10 v 0.90 39.9 v 240 ma = 1.06 a i = in(min) 14 v 0.90 32.85 v 240 ma = 0.625 a v = 10 3.2 v + 0.85 v = 32.85 v out v i out out v in(max) step 4c: determining the inductor value. to ensure that the inductor operates in continuous conduction mode, the value of the inductor needs to be set such that the ? inductor ripple cur- rent is not greater than the average minimum input current. a first pass calculation for k ripple should be 30% of the maximum inductor current. i = i k l in(max) ripple i = 1.0 6a 0.3 = 0.318 a l l = 0.318 a 2 mhz 10 v 0.75 = 11.79 h l = i f ) l sw (v d ) in(min) max double-check to make sure that ? current ripple is less than i in(min) . i in(min) > ? di l 0.625 a > 0.159 a a good inductor value to use would be 10 h. step 4d: this step is used to verify that there is sufficient slope compensation for the inductor chosen. 6 a/s slope compensation value is applied inside the ic at 2 mhz switching frequency. the slope compensation at any switching frequency can be deter- mined by the following formula: slope comp = 6 a/s f sw 2 10 6 next, insert the inductor value used in the design: i = l(used) v d in(min) max l(used) f sw i = l(used) = 0.375 a 10 v 0.75 10 h 2 mhz required min slope = i s 10 l(used) -6 1 f sw (1 ? d ) max where s is taken from the following formula: s = 1 ? 0.18 d max s = 0.76 = 2.28 a/s required min slope = 0.375 0.7 610 -6 1 2 mhz ( 1?0.75) wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
30 if the required minimum slope is larger than the calculated slope compensation, the inductor value needs to be increased. note that the slope compensation value is in a/s the 1 10 -6 is constant multiplier. step 4e: determining the inductor current rating. i = i + (1/2) i l(min) in(max) = 1.25 a i = 1.0 6a+ l(min) 0.375 a 2 l step 5: to determine the resistor value for a switching frequency refer to the graph in figure 8. a 10 k w resistor will result in a 2 mhz switching frequency. step 6: choosing the proper output schottky diode. the diode needs to be chosen for three characteristics when it is used in led lighting circuitry. the most obvious two are the current rating of the diode and the reverse voltage rating. the reverse voltage rating should be larger than the maximum output v ovp . the peak current through the diode is: = 1.25 a i = 1.06 + d(pk) 0.375 a 2 i = i + d(pk) in(max) i l(used) 2 the other major factor in deciding the switching diode is the reverse current characteristic of the diode. this characteristic is especially important when pwm dimming is implemented. during pwm off-time, the boost converter is not switching. this results in a slow bleeding off of the output voltage due to leakage currents. i r or reverse current can be a large contributor espe- cially at high temperatures. the reverse current of the selected diode varies between 1 and 100 a. for higher efficiency, use a small forward voltage drop diode. for lower high-frequency noise, choose a small junction capacitor diode. step 7: choosing the output capacitors. the output capacitors need to be chosen such that they can provide filtering for both the boost converter and for the pwm dimming function. the biggest factor that contributes to the size of the output capacitor is pwm dimming frequency and the pwm duty cycle. another major contributor is leakage current (i lk ). this current is the combina- tion of the ovp current sense as well as the reverse current of the boost diode. in this design, the pwm dimming frequency is 200 hz; the minimum duty cycle is 0.02%. typically, the voltage variation on the output during pwm dimming needs to be less than 250 mv (v cout ) so there is no audible hum. c = i out lk (1?minimum dimming duty cycles) pwm dimming frequency v cout the selected diode leakage current at a 150c junction tem- perature and 30 v output is 100 a, and the maximum leakage current through ovp pin is 1 a. the total leakage current can be calculated as follows: i lk = i lkg(diode) + i lkg(ovp) = 100 a + 1 a = 101 a c = 101 a out = 2 f (1 ? 0.02) 200 hz 0.250 v a capacitor larger than 2 f should be selected. due to degrada- tion of capacitance at dc voltages, a 4.7 f / 50 v capacitor is a good choice. vendor value part number murata 4.7 f / 50 v grm21bc18h475ke11k it is also necessary to note that if a high dimming ratio of 5000:1 must be maintained at lower input voltages, then larger out- put capacitors will be needed. 4 4.7 f / 50 v / x6s / 0805 capacitors are chosen; 0805 size is selected to minimize possible audible noise. the rms current through the capacitor is given by: c = i out(rms) out d + max i l(used) 1 ? d max i 12 in(max) c = 0.240 out(rms) = 0.424 a 0.75 + 0.375 1 ? 0.75 1.06 12 the output capacitor needs to have a current rating of at least 0.424 a. the capacitors selected in this design, 4 4.7 f / 50 v / x6s / 0805, have a combined current rating of more than 3 a current rating. wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
31 step 8: selection of input capacitor. the input capacitor needs to be selected such that it provides good filtering of the input volt- age waveform. a good rule of thumb is to set the input voltage ripple v in to be 1% of the minimum input voltage. the mini- mum input capacitor requirements are as follows: c = in i l(used) 8 f v sw in c = in = 0.234 f 0.375 a 8 2 mhz 0.1 v c = in(rms) c = in(rms) = 0.1 a i out i l(used) (1 ? d ) 12 max i in(max) = 0.1 a 0.240 a 0.375 a (1 ? 0.75) 12 1.06 a a good ceramic input capacitor with ratings of 50 v / 2.2 f or 50 v / 4.7 f will suffice for this application. vendor value part number murata 4.7 f / 50 v grm32er71h475ka88l murata 2.2 f / 50 v grm31cr71h225ka88l if long wires are used for the input, it is necessary to use a much larger input capacitor. a larger input capacitor is also required to have stable input voltage during line transients. combinations of aluminum electrolytic and ceramic capacitors can be used. step 9: choosing the input disconnect switch components. set the input disconnect current limit to 4.25 a. r= sc = 0.0259 0.11 v 4.25 a the r sc chosen is 0.024 ohms. therefore, the voltage drop across r sc is: r= adj v= 4.25 a 0.024 = 0.102 v sc vC v vsense(trip) sc i adj = 372 r= adj 0.11 v C 0.102 v 21.5 a a value of 383 w was chosen for this design. the disconnect switch q1 works as on or off. therefore, the r adj value is not really critical. for the input disconnect switch, an ao4421 6.2 a / 60 v p-chan- nel mosfet is selected. to achieve proper operation at low dimming ratios, connect an rc filter to the vout pin. use r = 10 k w and c = 47 pf. wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
32 47 f electrolytic 2.2 f 10 f 47 pf 10 f 1 f 100 pf 10 h 68 nf 0.024 383 280 158 k 10 k 10 k 11.8 k 10 k v= (4.5 to 40) v in *optional apwm clkout comp iset fset agnd gnd pgnd vdd vdd pwm led4 led1 led2 led3 ovp vin gate sw vout fa ult vsense q1 v> v out in a8519 figure 40: schematic showing calculated values from the design example above wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
33 package outline drawings for reference only ? not for tooling use (reference mo-153 act) dimensions in millimeters ? not to scale dimensions exclusive of mold ?ash, gate burrs, and dambar protrusions exact case and lead con?guration at supplier discretion within limits shown d a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 20x 0.65 bsc 0.25 bsc 21 1 20 6.50 0.10 4.40 0.10 3.00 3.00 4.20 4.20 6.40 0.20 gauge plane seating plane a b 0.45 1.70 20 21 b 6.10 0.65 c d exposed thermal pad (bottom surface) c pcb layout reference view nnnnnnn yyww lllllll standard branding reference view = device part number = supplier emblem = last two digits of year of manufacture = we ek of manufacture = lot number n y w l terminal #1 mark area reference land pattern layout (reference ipc7351 sop65p640x110-21m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) branding scale and appearance at supplier discretion figure 41: package lp: 20-pin, 0.65 mm pin pitch tssop with exposed thermal pad wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
34 figure 42: package et: 28-pin qfn with exposed thermal pad for reference only ? not for tooling use (reference jedec mo-220vhhd-1) dimensions in millimeters ? not to scale exact case and lead con?guration at supplier discretion within limits shown 0.25 +0.05 ?0.07 0.55 +0.20 ?0.10 0.50 0.90 0.10 c 0.08 29x seating plane c a b c 28 2 1 a 28 1 2 b 3.15 3.17 3.17 3.15 0.28 1 28 0.50 1.35 5.05 5.05 c 5.00 0.10 5.00 0.10 d d pcb layout reference view terminal #1 mark area exposed thermal pad (reference only, terminal #1 identi?er appearance at supplier discretion) reference land pattern layout (reference ipc7351 qfn50p500x500x100-29v1m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) coplanarity includes exposed thermal pad and terminals wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
35 for the latest version of this document, visit our website: www.allegromicro.com revision history number date description C september 10, 2014 initial release 1 october 24, 2014 lowered minium f sw (when using r fset ) to 200 khz and sync down to 260 khz. 2 march 18, 2015 revised ovp thresholds and oscillator frequencies. 3 may 19, 2015 added a8519-1 variant. 4 june 10, 2015 fixed typo on page 2; revised fset pin voltage typical spec. 5 november 4, 2015 amended enabling the ic (page 12) and synchronization (page 15) of functional description; inserted figures 18 and 19; updated selection guide table (page 2); corrected 2nd typical application drawing (page 9) 6 january 8, 2016 amended powering up: boost output undervoltage protection (page 13) 7 october 24, 2016 updated input overcurrent protection and disconnect switch section (page 22) copyright ?2016, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. wide input voltage range, high-efficiency, fault-tolerant led driver a8519 and a8519-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com

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